1. Technical Field
Example embodiments relate to a method of manufacturing a semiconductor device, and more particularly to a method of decomposing a layout of a semiconductor device.
2. Description of Related Art
In manufacturing a high density semiconductor device, a double patterning technology (DPT) process is generally used to avoid a conflict between patterns included in a layout of the semiconductor device. In the DPT process, a layout of a semiconductor device is decomposed into two patterns, and a wiring pattern is formed on a substrate by performing a lithography process on the substrate two times using the two patterns.
Recently, a triple patterning technology (TPT) process, in which a layout of a semiconductor device is decomposed into three patterns, and a wiring pattern is formed on a substrate by performing a lithography process on the substrate three times using the three patterns, and a quadruple patterning technology (QPT) process, in which a layout of a semiconductor device is decomposed into four patterns, and a wiring pattern is formed on a substrate by performing a lithography process on the substrate four times using the four patterns, have been developed.
As described above, a layout of a semiconductor device may be decomposed into a plurality of decomposed patterns to perform the DPT process, the TPT process or the QPT process. However, when pattern densities of the plurality of decomposed patterns are different from each other, a critical dimension uniformity may be affected and a loading effect may increase while performing a mask manufacturing process and an etching process based on the plurality of decomposed patterns.